Engineering Plan Engineering Plan SC312 Final recrudesce 11/7/04 *Names* We plan to give the basal multi-cycle processor design as shown in the textbook, as tight as pipelining and jump and link. The toughest part of this design testament be the datapath control, for which we volition be using a FSM. The ALU leave alone implement add, sub, and, or, sll, and slt functions though a separate block is typically used for shift operations, we felt that putting sll and srl in the ALU would transfer our design. All other basic functions (lw, sw, lui, beq, bne, j) will be hold as show in the textbook.
The processor will want two main stages: load instructions into store and implement instructions. Special instruction codes will be defined as stall and stop execution to work in reefer with the FSM. The global reset will set all memory board and registers to 0, and put the FSM in load instructions mode. We would mistakable to use one memory module to store some(prenominal) instruct...If you want to get a full essay, order it on our website:
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