Engineering Plan Engineering Plan SC312 Final realize 11/7/04 *Names* We plan to accomplish the base multi-cycle processor design as shown in the textbook, as close to as pipelining and jump and link. The toughest part of this design volition be the datapath control, for which we volition be using a FSM. The ALU go out implement add, sub, and, or, sll, and slt functions though a separate block is typically used for shift operations, we felt that putting sll and srl in the ALU would switch our design. All other basic functions (lw, sw, lui, beq, bne, j) will be utilize as show in the textbook.
The processor will drive two main stages: load instructions into store and implement instructions. Special instruction codes will be defined as stall and stop execution to work in coalition with the FSM. The global reset will set all depot and registers to 0, and put the FSM in load instructions mode. We would corresponding to use one memory module to store some(prenominal) instruct...If you want to get a full essay, order it on our website:
OrderCustomPaper.comIf you want to get a full essay, visit our page:
write my paper
No comments:
Post a Comment